Exemplary embodiments of the present invention relate to a semiconductor memory device and an operating method thereof, and more particularly, to technology for reducing a write to read command time interval (tWTR_CMD) between a write command and a read command of a semiconductor memory device.
FIG. 1 is a timing diagram illustrating the operation of a conventional memory device upon receiving a write command WRITE and a read command READ in succession.
In the following exemplary description, the additive latency (AL) has been set to 0, the column address strobe (CAS) write latency (CWL) has been set to 9, the CAS latency (CL) has been set to 13, and a burst length (BL) has been set to 4. The AL represents additive latency for a post-CAS operation; the CWL is obtained by subtracting the AL from the write latency (WL), the WL being the latency from the input of the write command WRITE to the input of corresponding write data from outside of the memory device; the CL represents the latency from the input of the read command READ to the output of corresponding data from the memory device; and the BL represents the number of data units outputted in series.
First of all, the write command WRITE is inputted to the memory device. Then, after the passage of 9 clocks corresponding to the WL, write data are inputted through a DQ pad from outside of the memory device. Since the BL is set to 4, 4 units of data are continuously inputted through the DQ pad during 2 clocks. The write data inputted through the DQ pad are arranged and then transmitted to a memory cell region through a data bus DATA BUS and are stored in the memory cell region. In FIG. 1, the write data loaded onto the data bus DATA BUS are represented by iDATA WT.
After the write data are inputted through the DQ pad and after the passage of the tWTR, the read command READ is inputted, the tWTR being defined as a time period from the input of the write data to the input of the read command READ. Then, the data stored in the memory cell region are read out and the read data are transferred to the DQ pad through the data bus DATA BUS. In FIG. 1, the read data loaded onto the data bus DATA BUS are represented by iDATA RD. The read data transferred to the DQ pad are arranged and then outputted outside of the memory device depending on the CL.
If the memory device operates as described above, the read command READ should be inputted after the passage of at least 16 clocks from a point in time where the write command WRITE has been inputted. If the read command READ is inputted before the passage of 16 clocks from the point in time where the write command WRITE has been inputted as the tWTR becomes shorter, a collision may occur on the data bus DATA BUS between the read data iDATA RD and the write data iDATA WT and thus, the data may vanish.
In the conventional semiconductor memory device, the read command READ should be inputted after the passage of a long time period from the point in time where the write command WRITE has been inputted. As a result, the performance of the semiconductor memory device is deteriorated.